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First-Principles Engineering

Fundamentals to Frontier AI: An Engineering Odyssey

A systematic public engineering log decomposing computer systems from the ground up: C memory allocators, cache coherence, and Linux event loops, bridging directly into modern inference serving, GPU memory management, and autonomous agent swarms.

5
Core Phases
Week 1
Active Module
100%
Open Source
Zero
Black Boxes
PHASE 1 • WEEK 1 Active Build

Memory Architecture & Custom Allocators

Before we can understand GPU VRAM bottlenecks, KV-cache paging, or high-throughput LLM serving, we must demystify how computers actually allocate, align, and address physical and virtual memory.

C11 Virtual Memory AddressSanitizer PyTorch CUDA Allocator Mechanical Sympathy

Day 1: Virtual Memory Layout & Struct Alignment

✓ Completed

Today we mapped out the 64-bit Linux process virtual address space (Text, Data, BSS, Heap, Stack) and measured the mechanical penalty of memory alignment and silent compiler struct padding.

The Silicon-to-Synapse Bridge (Why this matters for AI):

Tensors in PyTorch/CUDA are contiguous blocks aligned to 256-byte or 512-byte boundaries for vectorized memory coalescing. When activation tensors and KV-cache blocks fragment memory, an inference pipeline throws "CUDA: Out of Memory" even when nvidia-smi shows gigabytes of total free VRAM. Understanding allocator coalescence is the bedrock of GPU optimization.

// Comparing unpadded vs optimized struct layout: struct UnpaddedStruct { char a; double b; int c; char d; }; // 24 bytes (10 bytes wasted!) struct OptimizedStruct { double b; int c; char a; char d; }; // 16 bytes (33% memory saved!)
View Code on GitHub →

Upcoming Week 1 Sprints:

  • Day 2: Raw Syscalls & The Program Break (sbrk bump allocator)
  • Day 3: Metadata Headers & Free-List Traversal (malloc/free)
  • Day 4: External Fragmentation & Boundary-Tag Coalescence
  • Day 5: Microbenchmarks: my_malloc vs glibc ptmalloc
  • Weekend Capstone: Synthesis essay & Substack/Medium release